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Table-Top Demos and Corporate Support

Scope -- Submissions -- Key Dates -- Additional Information -- Committee

Scope

The 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs). While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike.

3D-TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the Test Technology Technical Council (TTTC) of the IEEE Computer Society.

Submissions

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Table-Top Demos – The 3D-TEST Workshop offers the opportunity to present Table-Top Demos during the workshop. Table-Top Demo participants get a table and electricity outlet provided by the workshop. A Table-Top Demo presentation may include displaying slides or demoing tools. Typical content may be comprised of technical descriptions, case studies, best practices, and user testimonials of products or solutions. These presentations will be listed in the workshop program booklet along with the regular paper sessions, and should be targeted to the workshop’s technical audience. Table-Top Demos differ from other workshop presentations in that a company name, logo, and product name may be mentioned explicitly. Proposal selection is based on technical content and relevance to 3D-TEST audience and topics. Table-Top Demo tables will be assigned in a first-come-first-served order, but priority will be given to Corporate Supporters (see below). If you are interested in presenting a Table-Top Demo, please contact the workshop’s Program Chair Erik Jan Marinissen at <erik.jan.marinissen@imec.be.>

Corporate Support – Companies are invited to provide financial support to the 3D-TEST Workshop. In return, the supporting corporations will be recognized by the workshop in various ways, including: display corporate logo on workshop’s website, program booklet, projection screen, Electronic Workshop Digest, etc. Corporate supporters get priority in the assignment of available Table-Top Demos. For additional details, please contact the workshop’s Finance Chair Bill Eklow at <beklow@cisco.com>.

Key Dates

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Submission deadline: August 21, 2015

Notification of acceptance: September 4, 2015

Camera-ready material: September 20, 2015

Additional Information

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General Chair:

Yervant Zorian

Synopsys

700 East Middlefield Road Mountain View, CA, USA

Tel.: +1 (650) 584-7120

yervant.zorian@synopsys.com

Program Chair:

Erik Jan Marinissen

IMEC

Kapeldreef 75

B-3001 Leuven, Belgium

Tel.: +32 16 28-8755

erik.jan.marinissen@imec.be

Program Vice-Chair:

Shi-Yu Huang

National Tsing-Hua University 101, Sec. 2, Kuang-Fu Road HsinChu, Taiwan

Tel.: +886 3-573-1147

syhuang@ee.nthu.edu.tw

Committee

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General Chair:

Y. Zorian – Synopsys (US)

Program Chair / Vice Chair:

E.J. Marinissen – IMEC (BE) S.-Y. Huang – NTHU (TW)

Finance Chair:

B. Eklow – Cisco Systems (US)

Panel Chair:

S.K. Goel – TSMC (US)

Publication Chair:

L. Ciganda – Politecnico di Torino (IT)

Publicity Chair:

F. von Trapp – 3DInCites (US)

Web Chair:

G. Jervan – Tallinn Univ. of Techn. (EE)

Arrangements Chair:

J. Potter – ASSET Intertech (US)

Program Committee Members:

S. Adham – TSMC (CAN)
V. Agrawal – Auburn Univ. (US)
S. Bhatia – Google (US)
K. Chakrabarty – Duke Univ. (US)
S. Chakravarty – Intel (US)
E. Cormack – DfT Solutions (UK)
A. Cron – Synopsys (US)
A. Crouch – ASSET InterTech (US)
P. Franzon – NC State Univ. (US)
S. Hamdioui – TU Delft (NL)
M. Higgins – Analog Devices (IRL) C.-L. Hsu – ITRI (TW)
M. Hutner – Teradyne (CAN)
L. Jiang – Shanghai JT Univ (CN)
H. Jiao – TU Eindhoven (NL)
H. Jun – SK hynix (KR)
S. Kameyama – Fujitsu (JP)
M. Knox – IBM (US)
M. Laisne – Qualcomm (US)
C.M. Li – NTU (TW)
M. Loranger – FormFactor (US)
A. Majumdar – Xilinx (US)
T.M. Mak – GlobalFoundries (US)
T. McLaurin – ARM (US)
B. Nadeau-Dostie – Mentor Graph. (US) B. Noia – AMD (US)
C. Papameletis – Cadence (US)
R. Parekhji – Texas Instruments (IN)
B. Patti – Tezzaron Semiconductor (US) M. Ricchetti – Synopsys (US)
S. Shaikh – Broadcom (US)
K. Smith – Cascade Microtech (US)
R. Vallauri – Technoprobe (IT)
P. Vivet – CEA-Leti (FR)
M. Wahl – Univ. Siegen (DE)

For more information, visit us on the web at: http://3dtest.tttc-events.org

The 6th IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).